SI5013 Datasheet, PDF (13/24 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
eliminates the need to externally configure the device to
operate with a particular reference clock. The REFCLK
frequency should be 19.44, 77.76, or 155.52 MHz with a
frequency accuracy of ±100 ppm.
4.6. Lock Detect
The Si5013 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The operation of the lock-detector
depends on the reference clock option used.
When an external reference clock is provided, the circuit
compares the frequency of a divided-down version of
the recovered clock with the frequency of the applied
reference clock (REFCLK). If the recovered clock
frequency deviates from that of the reference clock by
the amount specified in Table 4 on page 9, the PLL is
declared out of lock, and the loss-of-lock (LOL) pin is
asserted. In this state, the PLL will periodically try to
reacquire lock with the incoming data stream. During
reacquisition, the recovered clock frequency (CLKOUT)
drifts over a ±600 ppm range relative to the applied
reference clock and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, there is the
possibility that the PLL will not drift enough to render an
out-of-lock condition, even if the data is removed from
inputs.
In applications requiring a more stable output clock
during out-of-lock conditions, the lock-to-reference
(LTR) input can be used to force the PLL to lock to the
externally supplied reference.
In the absence of an external reference, the lock detect
circuitry uses a data quality measure to determine when
frequency lock has been lost with the incoming data
stream. During reacquisition, CLKOUT may vary by
approximately ±10% from the nominal data rate.
4.8. Loss-of-Signal
The Si5013 indicates a loss-of-signal condition on the
LOS output pin when the input peak-to-peak signal level
on DIN falls below an externally controlled threshold.
The LOS threshold range is specified in Table 3 on
page 8 and is set by applying a voltage on the LOS_LVL
pin. The graph in Figure 6 illustrates the LOS_LVL
mapping to the LOS threshold. The LOS output is
asserted when the input signal drops below the
programmed peak-to-peak value. If desired, the LOS
function may be disabled by grounding LOS_LVL or by
adjusting LOS_LVL to be less than 1 V.
40 mV
30 mV
15 mV
40 mV/V
0 mV
0V
1.00 V
1.50 V
1.875 V
2.25 V 2.5 V
LOS_LVL (V)
Figure 6. LOS_LVL Mapping
R1
Set LOS
Level
R2
3 _{LOS_LVL}
Si5013
10k
CDR
4.7. Lock-to-Reference
The LTR input can be used to force a stable output
clock when an alarm condition, like LOS, exists. In
typical applications, the LOS output is tied to the LTR
input to force a stable output clock when the input data
signal is lost. When LTR is asserted, the DSPLL is
prevented from acquiring the data signal present on
DIN. The operation of the LTR control input depends on
which reference clocking mode is used.
When an external reference clock is present, assertion
of LTR forces the DSPLL to lock CLKOUT to the
provided reference. If no external reference clock is
used, LTR forces the DSPLL to hold the digital
frequency control input to the VCO at the last value.
This produces a stable output clock as long as supply
and temperature are constant.
9
LOS
LOS Alarm
Figure 7. LOS Signal Hysteresis
In many applications it is desirable to produce a fixed
amount of signal hysteresis for an alarm indicator such
as LOS, since a marginal data input signal could cause
intermittent toggling, leading to false alarm status.
When it is anticipated that very low-level DIN signals will
be encountered, the introduction of an adequate
amount of LOS hysteresis is recommended to minimize
any undesirable LOS signal toggling. Figure 7 illustrates
a simple circuit that may be used to set a fixed level of
LOS signal hysteresis for the Si5013 CDR. The value of
Rev. 1.4
13