C8051F32X Datasheet, PDF (99/256 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16k ISP FLASH MCU Family

C8051F320/1
10. RESET SOURCES
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External Port pins are forced to a known state
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled during and after
the reset. For VDD Monitor and Power-On Resets, the /RST pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator.
Refer to Section “13. Oscillators” on page 117 for information on selecting and configuring the system clock
source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source (Section
“20.3. Watchdog Timer Mode” on page 246 details the use of the Watchdog Timer). Program execution begins at
location 0x0000.
Figure 10.1. Reset Sources
VDD
Px.x
Px.x
XTAL1
XTAL2
Internal
Oscillator
Clock
Multiplier
External
Oscillator
Drive
Supply
Monitor
+
-
Enable
Comparator 0
+
-
C0RSEF
Power On
Reset
'0'
Missing
Clock
Detector
(one-
shot)
EN
PCA
WDT
EN
Software Reset (SWRSF)
Errant
FLASH
Operation
(wired-OR)
Reset
Funnel
System
Clock
Clock Select
CIP-51
Microcontroller ^{System Reset}
Core
Extended Interrupt
Handler
USB
Controller
VBUS
Transition
/RST
Rev. 1.1
99