C8051F32X Datasheet, PDF (227/256 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16k ISP FLASH MCU Family

C8051F320/1
19.2.3. USB Start-of-Frame Capture
When T2SOF = ‘1’, Timer 2 operates in USB Start-of-Frame (SOF) capture mode. When T2SPLIT = ‘0’, Timer 2
counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents of the Timer 2 reg-
isters (TMR2H:TMR2L) are latched into the Timer 2 Reload registers (TMR2RLH:TMR2RLL). A Timer 2 interrupt
is generated if enabled. This mode can be used to calibrate the system clock or external oscillator against the known
USB host SOF clock.
Figure 19.13. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’)
TMR2CN
TTTTTT T
FFF22R 2
2 2 2SS2 X
HL LOP C
EFL L
NI K
T
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
0
TR2
1
TL2
Overflow
To SMBus
TCLK _{TMR2L TMR2H}
To ADC,
SMBus
USB
Start-of-Frame
(SOF)
Capture
TMR2RLL TMR2RLH
Enable
Interrupt
When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter counts up
independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents of the Timer 2 reg-
isters are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A Timer 2 interrupt is generated if
enabled.
Figure 19.14. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’)
TMR2CN
TTTTTT T
FFF22R 2
2 2 2SS2 X
HL LOP C
EFL L
NI K
T
SYSCLK / 12
0
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
TMR2RLH ^Capture
Enable
Interrupt
External Clock / 8
1
0
TCLK
TR2
TMR2H
To SMBus
1
SYSCLK
1
0
Capture
TMR2RLL
TCLK _TMR2L
To ADC,
SMBus
USB
Start-of-Frame
(SOF)
Rev. 1.1
227