C8051F32X Datasheet, PDF (212/256 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16k ISP FLASH MCU Family

C8051F320/1
Figure 18.10. SPI0CKR: SPI0 Clock Rate Register
R/W
SCR7
Bit7
R/W
SCR6
Bit6
R/W
SCR5
Bit5
R/W
SCR4
Bit4
R/W
SCR3
Bit3
R/W
SCR2
Bit2
R/W
SCR1
Bit1
R/W
Reset Value
SCR0 00000000
Bit0
SFR Address: 0xA2
Bits 7-0:
SCR7-SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured for master
mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the
following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value
held in the SPI0CKR register.
f_SCK = _2-----×-----₍--_S--^S--_P-^Y---_I-^S-0--^C-_C----^L-_K--^K--_R-----+-----1----₎
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f_SCK = _2---2--×-0---0-₍--40---0--+-0---0-1---₎
f_SCK = 200kHz
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Rev. 1.1