QL2007 Datasheet, PDF (9/10 Pages) List of Unclassifed Manufacturers – 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility

QL2007
AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00)
Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics are a design guide to provide initial timing estimates at
nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied
by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The
QuickChip/QuickTools/QuickWorks software incorporates data sheet AC Characteristics into the
design database for precise path analysis or simulation results following place and route.
Logic Cells
Symbol
Parameter
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [9]
Setup Time [9]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
Propagation Delays (ns)
3
Fanout [8]
1
2
3
4
8
1.4
1.7
2.0
2.3
3.5
1.8
1.8
1.8
1.8
1.8
0.0
0.0
0.0
0.0
0.0
0.8
1.1
1.4
1.7
2.9
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
1.4
1.7
2.0
2.3
3.5
1.2
1.5
1.8
2.1
3.3
1.9
1.9
1.9
1.9
1.9
1.8
1.8
1.8
1.8
1.8
Input-Only Cells
Symbol
tIN
tINI
tISU
tIH
tlCLK
tlRST
tlESU
tlEH
Propagation Delays (ns)
Parameter
Fanout [8]
1 2 3 4 8 12 24
High Drive Input Delay
2.5 2.6 2.6 2.7 3.5 4.6 5.8
High Drive Input, Inverting Delay
2.6 2.7 2.7 2.8 3.6 4.7 5.9
Input Register Set-Up Time
4.8 4.8 4.8 4.8 4.8 4.8 4.8
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock To Q
0.9 1.0 1.0 1.1 1.9 3.0 4.2
Input Register Reset Delay
0.8 0.9 0.9 1.0 1.8 2.9 4.1
Input Register clock Enable Set-Up Time 4.1 4.1 4.1 4.1 4.1 4.1 4.1
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
Notes:
[8] Stated timing for worst case Propagation Delay over process variation at VCC=5.0V and TA=25°C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
[9] These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic
cell including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.
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