QL2007 Datasheet, PDF (10/10 Pages) List of Unclassifed Manufacturers – 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility

QL2007
Clock Cells
Symbol
tACK
tGCKP
tGCKB
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Propagation Delays (ns)
Loads per Half Column [10]
1 2 3 4 8 10 13
2.2 2.2 2.3 2.4 2.5 2.6
1.2 1.2 1.2 1.2 1.2 1.2 1.2
1.5 1.6 1.6 1.7 1.8 1.9 2.0
I/O Cells
Propagation Delays (ns)
Symbol
Parameter
Fanout [8]
1
2
34
8
10
tI/O
Input Delay (bidirectional pad)
1.8 2.1 2.4 2.7 3.9 4.6
tISU
Input Register Set-Up Time
4.8 4.8 4.8 4.8 4.8 4.8
tIH
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
tlOCLK Input Register Clock To Q
0.8 1.1 1.4 1.7 2.9 3.6
tlORST Input Register Reset Delay
0.7 1.0 1.3 1.6 2.8 3.5
tlESU
Input Register clock Enable Set-Up Time 4.1 4.1 4.1 4.1 4.1 4.1
tlEH
Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
Symbol
Parameter
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [11]
Output Delay Low to Tri-State [11]
Propagation Delays (ns)
Output Load Capacitance (pF)
30
50
75
100 150
2.6
3.0
3.6
4.1
5.2
2.8
3.3
3.9
4.5
5.7
2.1
2.6
3.1
3.7
4.8
2.6
3.3
4.1
4.9
6.5
2.9
3.3
Notes:
[10] The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
[11] The following loads are used for tPXZ:
1KΩ
tPHZ
5 pF
1KΩ
tPLZ
5 pF
3-34