QL2007 Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility

QL2007
3.3V and 5.0V pASIC^® 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. E
pASIC 2
HIGHLIGHTS
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device ³
-16-bit counter speeds exceeding 200 MHz
… 7,000
usable ASICgates,
-7,000 usable ASIC gates, 11,000 usable PLD gates, 174 I/Os
-3-layer metal ViaLink^® process for small die sizes
174 I/O pins -100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
QL2007
Block Diagram
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
480
Logic
Cells
3-25