QL2007 Datasheet, PDF (6/10 Pages) List of Unclassifed Manufacturers – 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility

QL2007
Pin
TDI
TRSTB
TMS
TCK
TDO
STM
I/ACLK
I/GCLK
I
I/O
VCC
GND
PIN DESCRIPTIONS
Function
Test Data In for JTAG
Active low Reset for JTAG
Test Mode Select for JTAG
Test Clock for JTAG
Test data out for JTAG
Special Test Mode
High-drive input and/or array
network driver
High-drive input and/or global
network driver
High-drive input
Input/Output pin
Power supply pin
Ground pin
Description
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
Hold LOW during normal operation. Connect to
ground if not used for JTAG.
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
Hold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.
Output that must be left unconnected if not used for JTAG.
Must be grounded during normal operation.
Can be configured as either or both.
Can be configured as either or both.
Use for input signals with high fanout.
Can be configured as an input and/or output.
Connect to 3.3V supply.
Connect to ground.
ORDERING
INFORMATION
QuickLogic
pASIC device
pASIC 2 device
part number
Speed Grade
X = quick
0 = fast
1 = faster
2 = fastest
QL 2007 - 1 PQ208 C
3-30
Operating Range
C = Commercial
I = Industrial
Package Code
PL84 = 84-pin PLCC
PF144 = 144-pin TQFP
PQ208 = 208-pin PQFP