NT256D64S8HA0G-6 Datasheet, PDF (9/13 Pages) List of Unclassifed Manufacturers – 184pin Two Bank Unbuffered DDR SDRAM MODULE

NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter
-6
Unit
Min.
Max.
tAC
DQ output access time from CK/ CK
-0.7
+0.7
ns
tDQSCK DQS output access time from CK/ CK
-0.7
+0.7
ns
tCH
CK high-level width
0.45
0.55
tCK
tCL
CK low-level width
0.45
0.55
tCK
tCK
Clock cycle time
CL=2.5
CL=2
6
12
ns
7.5
12
ns
tDH
DQ and DM input hold time
0.45
ns
tDS
DQ and DM input setup time
0.45
ns
tDIPW
DQ and DM input pulse width (each input)
1.75
ns
tHZ
Data-out high-impedance time from CK/ CK
-0.7
+0.7
ns
tLZ
Data-out low-impedance time from CK/ CK
-0.7
+0.7
ns
tDQSQ
DQS-DQ skew (DQS & associated DQ signals)
0.4
ns
Minimum half CLK period for any given cycle;
tHP
tCH or tCL
tCK
defined by CLK high(tCH ) or CLK low (tCL ) time
tQH
Data output hold time from DQS
tHP - 0.75ns
tCK
tDQSS
Write command to 1st DQS latching transition
0.75
1.25
tCK
tDQSL,H
DQS input low (high) pulse width
(write cycle)
0.35
tCK
tDSS
DQS falling edge to CK setup time (write cycle)
0.2
tCK
tDSH
DQS falling edge hold time from CK (write cycle)
0.2
tCK
tMRD
Mode register set command cycle time
2
tCK
tWPRES Write preamble setup time
0
ns
tWPST
Write postamble
0.40
0.60
tCK
tWPRE
Write preamble
0.25
tCK
tIH
Address and control input hold time (fast slew rate)
0.75
ns
tIS
Address and control input setup time (fast slew rate)
0.75
ns
tIH
Address and control input hold time (slow slew rate)
0.8
ns
tIS
Address and control input setup time (slow slewrate)
0.8
ns
tIPW
Input pulse width
2.2
ns
tRPRE
Read preamble
0.9
1.1
tCK
tRPST
Read postamble
0.40
0.60
tCK
tRAS
Active to Precharge command
42
120,000
ns
tRC
Active to Active/Auto-refresh command period
60
ns
tRFC
Auto-refresh to Active/Auto-refresh command period
72
ns
tRCD
Active to Read or Write delay
18
ns
tRAP
Active to Read Command with Autoprecharge
18
ns
tRP
Precharge command period
18
ns
tRRD
Active bank A to Active bank B command
12
ns
tW R
Write recovery time
15
ns
(tWR/tCK )
tDAL
Auto precharge write recovery + precharge time
+
tCK
(tRP/tCK )
tWTR
Internal write to read command delay
1
tCK
tXSNR
Exit self-refresh to non-read command
75
ns
tXSRD
Exit self-refresh to read command
200
tCK
tREFI
Average Periodic Refresh Interval
15.6
µs
Notes
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4,15,16
1,2,3,4,15,16
1,2,3,4
1, 2, 3,4, 5
1, 2, 3,4, 5
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1, 2, 3,4, 7
1, 2, 3,4, 6
1,2,3,4
2, 3, 4,9, 11,12
2, 3, 4,9, 11,12
2, 3, 4,10, 11,12, 14
2, 3, 4,10, 11,12, 14
2, 3, 4,12
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1, 2, 3,4, 13
1,2,3,4
1,2,3,4
1,2,3,4
1, 2, 3,4, 8
Preliminary, 11/2001
9
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.