NT256D64S8HA0G-6 Datasheet, PDF(3/13 Page) List of Unclassifed Manufacturers – 184pin Two Bank Unbuffered DDR SDRAM MODULE

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NT256D64S8HA0G-6 Datasheet, PDF (3/13 Pages) List of Unclassifed Manufacturers – 184pin Two Bank Unbuffered DDR SDRAM MODULE

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NT256D64S8HA0G-6

256MB : 32M x 64

PC2700 Unbuffered DIMM

Input/Output Functional Description

Symbol

CK0 , CK1, CK2

CK0 , CK1 , CK2

CKE0, CKE1

S0 , S1

RAS , CAS , WE

VREF

VDDQ

BA0, BA1

A0 - A9

A10/AP

A11

DQ0 - DQ63,

DQS0 - DQS7

DQS9 - DQS16

VDD , VSS

SA0 â SA2

SDA

SCL

VDDSPD

Type

(SSTL)

Supply

(SSTL)

Supply

Polarity

Function

The positive line of the differential pair of system clock inputs which drives the input to the

Positive

on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising

Edge

edge of their associated clocks.

Negative The negative line of the differential pair of system clock inputs which drives the input to the

Edge on-DIMM PLL.

Active

High

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh

mode.

Active

Low

Enables the associated SDRAM command decoder when low and disables the command

decoder when high. When the command decoder is disabled, new commands are ignored

but previous operations continue.

Active When sampled at the positive rising edge of the clock, RAS , CAS , WE define the

Low operation to be executed by the SDRAM.

Reference voltage for SSTL-2 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

- Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,

autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

Active Data strobes: Output with read data, input with write data. Edge aligned with read data,

High centered on write data. Used to capture write data.

Power and ground for the DDR SDRAM input buffers and core logic

Address inputs. Connected to either VDD or VSS on the system board to configure the

Serial Presence Detect EEPROM address.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pullup.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pullup.

Serial EEPROM positive power supply.

Preliminary, 11/2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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