NT256D64S8HA0G-6 Datasheet, PDF (8/13 Pages) List of Unclassifed Manufacturers – 184pin Two Bank Unbuffered DDR SDRAM MODULE

NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Operating, Standby, and Refresh Currents
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
PC2700
Unit
Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;
I DD0
tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;
1160
mA
address and control inputs changing once per clock cycle
Operating Current : one bank; active / read / precharge; Burst = 2;
I DD1
tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;
address and control inputs changing once per clock cycle
1360
mA
I DD2P
Precharge Power-Down Standby Current :
all banks idle; power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)
240
mA
Idle Standby Current : CS ≥ VIH (MIN) ; all banks idle; CKE >= VIH(MIN) ;
I DD2N
tCK = tCK (MIN) ; address and control inputs changing once per clock cycle
560
mA
I DD3P
Active Power-Down Standby Current : one bank active;
power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)
240
mA
Active Standby Current : one bank; active / precharge; CS ≥ VIH (MIN) ;
CKE ≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS
I DD3N _{inputs changing twice per clock cycle;}
960
mA
address and control inputs changing once per clock cycle
Operating Current : one bank; Burst = 2; reads; continuous burst;
I DD4R
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
1800
mA
tCK = tCK (MIN) ; IOUT = 0mA
Operating Current : one bank; Burst = 2; writes; continuous burst;
I DD4W
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
1680
mA
tCK = tCK (MIN)
I DD5 Auto-Refresh Current :
t RC = t RFC (MIN)
t RC = 15.625 µs
2400
mA
252
mA
I DD6 Self-Refresh Current : CKE ≤ ?0.2V
32
mA
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2,4
1,2,3
Preliminary, 11/2001
8
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