JA32050 Datasheet, PDF (9/19 Pages) List of Unclassifed Manufacturers – 8-Bit MCU,ADC,LCD Controller

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JA32050
TS2
TS1
TS0
TMR1 Clock Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Ԧʳ Watchdog Timer
The clock source for watchdog timer (WDT) can be either internal RC (32kHz) or system clock/4;
decided by Bit 4 of WDTC register. When WDT is enabled, user shall reset (writing “1”) Bit 0 of
WDTCLR register within a specific time to prevent WDT overflow.
WDTCLR (W): 03h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
—
—
—
—
—
—
—
CLRWDT
WDTC (R/W): 04h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
—
—
—
WDTCLK
—
—
—
WDTEN
Bit 4 (WDTCLK): Select the WDT clock source
0=system clock/4 (Default) , 1= Internal RC clock
Bit0 (WDTEN): To enable/disable the WDT, 0= Disable (Default), 1= Enable
I/O Configuration
The I/O port A (PA) is dedicated to ADC circuit so that user cannot use PA for other use. Port B (PB) can be
used as normal input and output operations. For input operation, PB is non-latched , for output operation, all
the data are latched and remain unchanged till the output latch is re-written.
Each I/O port has its own control register (PAC, PBC) to control the input/output configuration.
Ԧʳ PA Configuration
PA control register specifies the characteristic of PA. Please refer to the table below:
Label Address
Function
R/W
PA
0Bh
PA data input/output
R/W
PAC
0Ch
PA direction control, 1=input 0=output
R/W
PAR
0Dh
PA pull-high resistor option, 1=With, 0=Without
R/W
Default
FF
FF
FF
In JA32050, PA is dedicated to ADC circuit, PA5 for ON/OFF control, PA6 for COMPO, PA4 for CHAR/DIS
(charge/discharge) control, others PA pins cannot be used. Please see the block diagram on first page for
reference.
Ԧʳ PB Configuration
For port B, they can be configured as follows:
Label Address
Function
PB
0Eh
PB data input/output
PBC
0Fh
PB direction control, 1=input 0=output
PBR
10h
PB pull-high resistor option, 1=With, 0=Without
R/W
R/W
R/W
R/W
Default
FF
FF
FF
Preliminary
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FAXΚ886-3-5770756
19-9
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Ver.0.0
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