JA32050 Datasheet, PDF(6/19 Page) List of Unclassifed Manufacturers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

JA32050 Datasheet, PDF (6/19 Pages) List of Unclassifed Manufacturers – 8-Bit MCU,ADC,LCD Controller

◁

JA32050

Power Configuration

POWERC

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

POWERC 00h LVFLAG DETEN

STOP

HALT

The system provides the HALT mode and the STOP mode for power saving:

Ô¦Ê³ HALT mode

Writing â1â to the HALT bit cause system enter HALT mode. In HALT mode, the system clock stop

running but the internal RC clock (32K) continuously keeps free running. The timer overflow, WDT

overflow, external interrupt (INTB) or PA,PB change state can wakeup the system to leave the HALT

mode. The HALT bit will be cleared to â0â automatically when system is awakened (STOP bit

unchanged).

Ô¦Ê³ STOP mode

Writing â 1â to the STOP bit causes system enter STOP mode. In STOP mode, both the system clock

and internal RC clock stop running. External interrupt (INTB) or PA,PB change state can wakeup the

system. The HALT bit and the STOP bit will be cleared to â0â automatically when system is awakened.

Ô¦Ê³ Low voltage

Writing â 1â to DETEN bit enable the low battery detector circuit of the system. If the low battery

situation is detected, the LVFLAG bit will be set to â1â by detector circuit. After writing the DETEN bit,

the user must insert 2 NOP instructions in the program before program reading the LVFLAG data.

External resistor shown below adjusts the low voltage level:

3'(7

/RZ9ROWDJH

'HWHFWRU&.7

/9)/$*

'(7(1

The table below is a reference for low voltage setting. If user set low voltage level at 2.15V then 40K ohm

resistor shall be used. When Vdd drops to 2.15V the LVFLAG will become â1â indicating the low battery

event.

Resistor

Vdd

PDET

LVFLAG

40 K

2.15V

0.699V

50 K

2.45V

0.899V

54 K

2.55V

0.97V

60 K

2.65V

1.09V

70 K

2.85V

1.27V

Reset and Wakeup

The system will be reset by the following conditions:

Ô¦Ê³ Power on

Ô¦Ê³ Reset pin activated (Low)

Ô¦Ê³ Illegal address generation

Ô¦Ê³ WDT overflow

Ô¦Ê³ VDD voltage lower than 1.8V

Preliminary

TELÎ886-3-5770755

FAXÎ886-3-5770756

19-6

E-mailÎsales@jaztek.com.tw

Ver.0.0

Web-siteÎwww.jaztek.com.tw

▷