JA32050 Datasheet, PDF (7/19 Pages) List of Unclassifed Manufacturers – 8-Bit MCU,ADC,LCD Controller

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JA32050
The system will be awakened from STOP mode or HALT mode by the following conditions:
Ԧʳ Timer/WDT overflow
Ԧʳ Level changes on PB input pins
The above situations will make system start running. The starting address depends on the INTF register
setting. If the global interrupt bit (INTE) is cleared and the corresponding interrupt bit is set, no wakeup
interrupt will be generated and program start running from next instruction in STOP mode or HALT mode. If
the global interrupt bit (INTE) is set, the system will execute the corresponding interrupt service routine first
then back to execute the next instruction in STOP mode or HALT mode.
Interrupt
In JA32050, the INTC register and the INTF register handle the interrupt operation. Setting or clearing the
INTC (interrupt control register) bits will enable or disable the interrupt function. The INTF (interrupt flag)
shows the current interrupt status.
The system will be interrupted by the following conditions:
Ԧʳ Timer/WDT overflow
Ԧʳ Level changes on PB input pins
Interrupt control register (INTC) definition is shown below:
INTC (R/W): 01h
Register Bit No.
0
1
2
INTC
3
4
5
6
7
Label
INTE
Reserved
TMR0
TMR1
PAI
PBI
Function
Global interrupt enable bit
(1= Enabled; 0 = Disabled)
Must be set to “0”
TMR0 interrupt Enable bit
(1= Enabled; 0 = Disabled)
TMR1 interrupt Enable bit
(1= Enabled; 0 = Disabled)
Port A change state interrupt Enable bit
(1= Enabled; 0 = Disabled)
Port B change state interrupt Enable bit
(1= Enabled; 0 = Disabled)
Reserved
Reserved
Interrupt Flag (INTF) definition is shown below:
INTF (R/W): 02h
Register Bit No.
0
1
INTF
2
3
4
5
6
7
Label
INTF
TMR0F
TMR1F
PAF
PBF
Function
External INT interrupt flag bit
(1= Active; 0 = Inactive)
TMR0 timer interrupt flag bit
(1= Active; 0 = Inactive)
TMR1 timer interrupt flag bit
(1= Active; 0 = Inactive)
Reserved
Port A change state interrupt flag bit
(1= Active; 0 = Inactive)
Port B change state interrupt flag bit
(1= Active; 0 = Inactive)
Reserved
Reserved
Preliminary
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