CY28447 Datasheet, PDF (8/21 Pages) List of Unclassifed Manufacturers – Clock Generator for Intel® Calistoga Chipset

CY28447
Byte 9: Control Register 9
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
1
1
0
Name
Description
RESERVED
RESERVED
S1
S0
RESERVED
RESERVED
27M_SS / LCD 96_100M SS Spread Spectrum Selection table:
S[1:0] SS%
‘00’ = –0.5%(Default value)
‘01’ = –1.0%
‘10’ = –1.5%
‘11’ = –2.0%
RESERVED
RESERVED, Set = 1
27M_SS
27M Spread Output Enable
0 = Disable (Tri-state), 1 = Enabled
27M_SS Spread Enable _{27M_SS Spread spectrum enable.}
0 = Disable, 1 = Enable.
RESERVED
RESERVED set = 0
Byte 10: Control Register 10
Bit
7
6
5
@Pup
1
1
1
Name
RESERVED
RESERVED
SRC[T/C]9
4
1
SRC[T/C]8
3
0
RESERVED
2
0
SRC[T/C]10
1
0
SRC[T/C]9
0
0
SRC[T/C]8
Byte 11: Control Register 11
Bit
7
@Pup
0
Name
RESERVED
6
HW
RESERVED
5
HW
RESERVED
4
HW
RESERVED
3
0
27M_SS / 27M_NSS
2
0
RESERVED
1
0
RESERVED
0
HW
RESERVED
Description
RESERVED, Set = 1
RESERVED, Set = 1
SRC[T/C]9 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]8 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED, Set = 0
Allow control of SRC[T/C]10 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]9 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]8 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Description
RESERVED
RESERVED
RESERVED
RESERVED
27-MHz (spread and non-spread) Output Drive Strength
0 = Low, 1 = High
RESERVED
RESERVED Set = 0
RESERVED
Rev 1.0, November 20, 2006
Page 8 of 21