CY28447 Datasheet, PDF (1/21 Pages) List of Unclassifed Manufacturers – Clock Generator for Intel® Calistoga Chipset

PRELIMINARY
CY28447
Clock Generator for Intel^® Calistoga Chipset
Features
• Compliant to Intel^® CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clock
• SRC clocks independently stoppable through
CLKREQ#[1:9]
• 96/100 MHz spreadable differential video clock
Block Diagram
• 33 MHz PCI clocks
• Buffered Reference Clock 14.318MHz
• Low-voltage frequency select inputs
• I²C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
CPU
SRC PCI REF DOT96 USB_48M LCD
27M
x2 / x3 x9/11 x5 x 2 x 1
x1
x1
x2
Pin Configuration
XIN
XOUT
SEL_CLKREQ
PCI_STP#
CPU_STP#
CLKREQ[1:9]#
ITP_SEL
FS[C:A]
14.318MHz
Crystal
PLL Reference
CPU
PLL
Divider
FCTSEL1
VTT_PWRGD#/PD
SDATA
SCLK
LVDS
PLL
Divider
Fixed
PLL
Divider
27M
PLL
I2C
Logic
Divider
VDD
REF[1:0]
IREF
VDD
CPUT[0:1]
CPUC[0:1]
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD
SRCT(1:9])
SRCC(1:9])
VDD
PCI[1:4]
VDD_PCI
PCIF0
VDD
SRCT0/100MT_SST
SRCC0/100MC_SST
VDD48
27M Spread
VDD48
DOT96T
DOT96C
VDD48
48M
VDD48
27M Non-spread
VDD_SRC
SRCC_9
SRCT_9
VSS_SRC
CPUC2_ITP / SRCC_10
CPUT2_ITP / SRCT_10
VDDA
VSSA
IREF
CPUC1
CPUT1
VDD_CPU
CPUC0
CPUT0
VSS_CPU
SCLK
SDATA
VDD_REF
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
CY28447
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VDD_SRC
SRCC_2
SRCT_2
SRCC_1
SRCT_1
VDD_SRC
SRCC_0 / LCD100MC
SRCT_0 / LCD100MT
CLKREQ1#
FSB/TEST_MODE
DOT96C / 27M_SS
DOT96T / 27M_NSS
VSS_48
48M / FSA
VDD_48
VTT_PWRGD# / PD
CLKREQ7#
PCIF0/ITP_SEL
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 21
www.SpectraLinear.com