CY28447 Datasheet, PDF (14/21 Pages) List of Unclassifed Manufacturers – Clock Generator for Intel® Calistoga Chipset

PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level.
Tsu
Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
CY28447
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
Figure 11. PCI_STP# Deassertion Waveform
VDD Clock Gen
Clock State State 0
0.2-0.3mS
Delay
State 1
Wait for
VTT_PW RGD#
Sample Sels
State 2
Device is not affected,
VTT_PW RGD# is ignored
State 3
Off
Clock Outputs
Off
Clock VCO
On
On
Figure 12. VTT_PWRGD# Timing Diagram
VDD_A = 2.0V
S0
Power Off
S1
Delay
>0.25mS
VTT_PWRGD# = Low
S2
Sample
Inputs straps
VDD_A = off
S3
Normal
Operation
VTT_PWRGD# = toggle
Wait for <1.8ms
Enable Outputs
Figure 13. Single-ended Load Configuration
Rev 1.0, November 20, 2006
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