CY28447 Datasheet, PDF (6/21 Pages) List of Unclassifed Manufacturers – Clock Generator for Intel® Calistoga Chipset

CY28447
Byte 3: Control Register 3
Bit
@Pup
7
0
Name
SRC7
6
0
SRC6
5
0
SRC5
4
0
SRC4
3
0
SRC3
2
0
SRC2
1
0
SRC1
0
0
SRC0
Byte 4: Control Register 4
Bit
@Pup
Name
7
0
LCD_96_100M[T/C]
6
0
DOT96[T/C]
5
0
4
0
3
0
RESERVED
RESERVED
PCIF0
2
1
CPU[T/C]2
1
1
CPU[T/C]1
0
1
CPU[T/C]0
Byte 5: Control Register 5
Bit
@Pup
7
0
Name
SRC[T/C]
6
0
CPU[T/C]2
5
0
CPU[T/C]1
4
0
CPU[T/C]0
3
0
2
0
SRC[T/C][9:1]
CPU[T/C]2
Description
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Description
LCD_96_100M[T/C] PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
RESERVED, Set = 0
RESERVED, Set = 0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Description
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#
asserted
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
SRC[T/C][9:1] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Rev 1.0, November 20, 2006
Page 6 of 21