CCD47-20 Datasheet, PDF (8/11 Pages) List of Unclassifed Manufacturers – High Performance CCD Sensor

DETAIL OF OUTPUT CLOCKING
7133A
R11
T_r
t_or
R12
R13
1R
OS
t_wx
t_dx
OUTPUT
VALID
RESET FEEDTHROUGH
SIGNAL
OUTPUT
LINE OUTPUT FORMAT
8 BLANK
15 DARK REFERENCE
* * ^{1024 ACTIVE OUTPUTS}
15 DARK REFERENCE
RECOMMENDED
D.C. CLAMP TIME
* = Partially shielded transition elements
7512
8 BLANK
CLOCK TIMING REQUIREMENTS
Symbol
T_i
t_wi
t_ri
t_fi
t_oi
t_dir
t_dri
T_r
t_rr
t_fr
t_or
t_wx
t_rx, t_fx
t_dx
Description
Image clock period
Image clock pulse width
Image clock pulse rise time (10 to 90%)
Image clock pulse fall time (10 to 90%)
Image clock pulse overlap
Delay time, S1 stop to R1 start
Delay time, R1 stop to S1 start
Output register clock cycle period
Clock pulse rise time (10 to 90%)
Clock pulse fall time (10 to 90%)
Clock pulse overlap
Reset pulse width
Reset pulse rise and fall times
Delay time, 1R low to R13 low
Min
2
1
0.1
t_ri
(t_ri+t_fi)/2
1
1
200
50
t_rr
20
30
0.2t_wx
30
Typical
5
2.5
0.5
0.5
0.5
2
1
1000
0.1T_r
0.1T_r
0.5t_rr
0.1T_r
0.5t_rr
0.5T_r
Max
see note 15
ms
see note 15
ms
0.2T_i
ms
0.2T_i
ms
0.2T_i
ms
see note 15
ms
see note 15
ms
see note 15
ns
0.3T_r
ns
0.3T_r
ns
0.1T_r
ns
0.3T_r
ns
0.1T_r
ns
0.8T_r
ns
NOTES
15. No maximum other than that necessary to achieve an acceptable dark signal at the longer readout times.
16. To minimise dark current, two of the I1 clocks should be held low during integration. I1 timing requirements are identical to
S1 (as shown above).
CCD47-20, page 8
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