CCD47-20 Datasheet, PDF (5/11 Pages) List of Unclassifed Manufacturers – High Performance CCD Sensor

CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS
PIN REF DESCRIPTION
1 SS
Substrate
2 ABD Anti-blooming drain (see note 10)
3 I13 Image area clock
4 I12 Image area clock
5 I11 Image area clock
6 SS
Substrate
7 OG
Output gate
8 RDL Reset transistor drain (left amplifier)
9–
No connection
10 OSL Output transistor source (left amplifier)
11 ODL Output transistor drain (left amplifier)
12 SS
Substrate
13 1RL Output reset pulse (left amplifier)
14 R13L Output register clock (left section)
15 R12L Output register clock (left section)
16 R11L Output register clock (left section)
17 R11R Output register clock (right section)
18 R12R Output register clock (right section)
19 R13R Output register clock (right section)
20 1RR Output reset pulse (right amplifier)
21 SS
Substrate
22 ODR Output transistor drain (right amplifier)
23 OSR Output transistor source (right amplifier)
24 –
No connection
25 RDR Reset transistor drain (right amplifier)
26 DG
Dump gate (see note 12)
27 SS
Substrate
28 S11 Storage area clock
29 S12 Storage area clock
30 S13 Storage area clock
31 ABG Anti-blooming gate
32 SS
Substrate
PULSE AMPLITUDE OR
DC LEVEL (V) (See note 9)
Min Typical Max
0
9
10
V_OD
8
12
15
8
12
15
8
12
15
0
9
10
1
3
5
15
17
19
–
see note 11
27
29
31
0
9
10
8
12
15
8
10
15
8
10
15
8
10
15
8
10
15
8
10
15
8
10
15
8
12
15
0
9
10
27
29
31
see note 11
–
15
17
19
–
0
–
0
9
10
8
12
15
8
12
15
8
12
15
0
0
5
0
9
10
MAXIMUM RATINGS
with respect to V_SS
–
70.3 to +25 V
+20 V
+20 V
+20 V
–
+20 V
70.3 to +25 V
–
70.3 to +25 V
70.3 to +35 V
–
+20 V
+20 V
+20 V
+20 V
+20 V
+20 V
+20 V
+20 V
–
70.3 to +35 V
70.3 to +25 V
–
70.3 to +25 V
+20 V
–
+20 V
+20 V
+20 V
+20 V
–
Maximum voltages between pairs of pins:
pin 10 (OSL) to pin 11 (ODL) . . . . . . +15 V
pin 22 (ODR) to pin 23 (OSR) . . . . . . +15 V
Maximum output transistor current . . . . . 10 mA
NOTES
9. Readout register clock pulse low levels +1 V; other clock low levels 0+0.5 V.
10. Drain not incorporated, but bias is still necessary.
11. 3 to 5 V below OD. Connect to ground using a 2 to 5 mA current source or appropriate load resistor (typically 5 to 10 kO).
12. Non-charge dumping level shown. For operation in charge dumping mode, DG should be pulsed to 12 + 2 V.
13. All devices will operate at the typical values given. However, some adjustment within the minimum to maximum range may be
required for to optimise performance for critical applications. It should be noted that conditions for optimum performance may
differ from device to device.
14. With the R1 connections shown, the device will operate through the left-hand output only. In order to operate from both
outputs R11(R) and R12(R) should be reversed.
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CCD47-20, page 5