W78E365 Datasheet, PDF (6/40 Pages) Winbond – 8-BIT MICROCONTROLLER

W78E365
6. FUNCTIONAL DESCRIPTION
The W78E365 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
6.1 RAM
The internal data RAM in the W78E365 is 256+1K bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways.
• RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
• RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
R1 of the selected registers bank.
• AUX-RAM 0H − 3FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 3FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is enable after a reset. Setting the
bit 4 in CHPCON register will enable the access to AUX-RAM. When executing from internal
program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .
Example:
CHPENR
CHPCON
XRAMAH
REG
REG
REG
F6H
BFH
A1H
MOV
MOV
ORL
MOV
MOV
MOV
MOV
MOVX
MOV
MOV
MOVX
MOV
MOV
MOVX
MOV
MOVX
CHPENR, #87H
CHPENR, #59H
CHPCON, #00010000B ; enable AUX-RAM
CHPENR, #00H
XRAMAH, #01H
; internal high address
R0, #23H
A, #55H
@R0, A
; Write 55h data to 0123h AUX-RAM address.
XRAMAH, #02H
R1, #FFH
; Read data from 02FFh AUX-RAM address.
A, @R1
DPTR, #0134H
A, #78H
@DPTR, A
; Write 78h data to 0134h AUX-RAM address.
DPTR, #7FFFH
A, @DPRT
; Read data from the external 7FFFh address SRAM
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