SI5320 Datasheet, PDF (6/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
Table 2. DC Characteristics, V_DD = 3.3 V
(V_DD33 = 3.3 V ±5%, T_A = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Supply Current 1
I_DD
Clock in = 622.08 MHz
Clock out = 19.44 MHz —
141 155
mA
Supply Current 2
I_DD
Clock in = 19.44 MHz
Clock out = 622.08 MHz —
135 145
mA
Power Dissipation Using 3.3 V Supply
Clock Output
P_D
Clock in = 19.44 MHz
Clock out = 622.08 MHz —
445 479 mW
Common Mode Input Voltage^1,2,3
(CLKIN)
V_ICM
1.0
1.5
2.0
V
Single-Ended Input Voltage^2,3,4
(CLKIN)
V_IS
See Figure 1A
200
—
500⁴ mV_PP
Differential Input Voltage Swing^2,3,4
V_ID
(CLKIN)
See Figure 1B
200
—
500⁴ mV_PP
Input Impedance
(CLKIN+, CLKIN–)
Differential Output Voltage Swing
(CLKOUT)
Output Common Mode Voltage
(CLKOUT)
R_IN
V_OD
V_OCM
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line
—
80
—
kΩ
816 906 1100 mV_PP
1.4
1.8
2.2
V
Output Short to GND (CLKOUT)
I_SC(–)
–60
—
—
mA
Output Short to V_DD25 (CLKOUT)
I_SC(+)
—
15
—
mA
Input Voltage Low (LVTTL Inputs)
V_IL
—
—
0.8
V
Input Voltage High (LVTTL Inputs)
V_IH
Input Low Current (LVTTL Inputs)
I_IL
Input High Current (LVTTL Inputs)
I_IH
Internal Pulldowns (All LVTTL Inputs)
I_pd
2.0
—
—
V
—
—
50
µA
—
—
50
µA
—
—
50
µA
Input Impedance (LVTTL Inputs)
R_IN
50
—
—
kΩ
Output Voltage Low (LVTTL Outputs)
V_OL
I_O = .5 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs) V_OH
I_O = .5 mA
2.0
—
—
V
Notes:
1. The Si5320 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac
coupled to ground.
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5320 device can operate with input clock swings as high as 1500 mV_PP, Silicon Laboratories recommends
maintaining the input clock amplitude below 500 mV_PP for optimal performance.
6
Rev. 2.3