SI5320 Datasheet, PDF (18/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
minimizes the output clock jitter variation from board to
board, providing more consistent system level jitter
performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. (See Table 7.) Lower bandwidth
selection settings result in more jitter attenuation of the
incoming clock but may result in higher jitter generation.
Table 4 on page 9 gives the 3 dB bandwidth and
peaking values for specified BWSEL settings. Figure 6
shows the jitter transfer curve mask.
Jitter
Transfer
Jitter
Jitte
Ou
r In
t
(s)
0 dB
Peaking
–20 dB/dec.
F_BW
f_Jitter
Figure 6. PLL Jitter Transfer Mask/Template
2.3.3. Jitter Tolerance
Jitter tolerance for the Si5320 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. The tolerance is a
function of the jitter frequency, because tolerance
improves for lower input jitter frequency. See Figure 7.
Input
Jitter
A m p litu d e
–20 dB/dec.
Excessive Input Jitter Range
2.5. Hitless Recovery from Digital Hold
When the Si5320 device is locked to a valid input clock,
a loss of the input clock causes the device to
automatically switch to digital hold mode. When the
input clock signal returns, the device performs a
“hitless” transition from digital hold mode back to the
selected input clock. That is, the device performs
“phase build-out” to absorb the phase difference
between the internal VCO clock operating in digital hold
mode and the new/returned input clock. The maximum
phase step size seen at the clock output during this
transition and the maximum slope for this phase step
are given in Table 4 on page 9.
This feature can be disabled by asserting the
FXDDELAY pin. When the FXDDELAY pin is high, the
output clock is phase and frequency locked with a
known phase relationship to the input clock.
Consequently, any abrupt phase change on the input
clock propagates through the device, and the output
slews at the selected loop bandwidth until the original
phase relationship is restored.
Note: When the DBLBW is asserted, hitless recovery must
also be disabled by driving FXDDELAY high for proper
operation.
m_PT
t_{PT_MTIE}
10 ns
F_BW
f_{Jitter In}
Figure 7. Jitter Tolerance Mask/Template
2.4. Digital Hold of the PLL
When no valid input clock is available, the Si5320
digitally holds the internal oscillator to its last frequency
value. This provides a stable clock to the system until an
input clock is again valid. This clock maintains very
stable operation in the presence of constant voltage and
temperature. The frequency accuracy specifications for
digital hold mode are given in Table 4 on page 9.
Recovery from
digital hold
Figure 8. Recovery from Digital Hold
2.6. Loss-of-Signal Alarm
The Si5320 has loss-of-signal (LOS) circuitry that
constantly monitors the CLKIN input clock for missing
pulses. The LOS circuitry sets a LOS output alarm
signal when missing pulses are detected.
The LOS circuitry operates as follows. Regardless of
the selected input clock frequency range, the LOS
circuitry divides down the input clock into the 19 MHz
range. The LOS circuitry then over-samples this
divided-down input clock to search for extended periods
of time without input clock transitions. If the LOS
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Rev. 2.3