SI5320 Datasheet, PDF (27/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320
Table 11. Si5320 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
B1
BWSEL[0]
I*
LVTTL
Bandwidth Select.
C1
BWSEL[1]
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note: The loop filter bandwidth will be twice the value
indicated when DBLBW is set high.
E8
CAL_ACTV
O
LVTTL
Calibration Mode Active.
This output is driven high during the DSPLL self-cal-
ibration and the subsequent initial lock acquisition
period.
H4
VALTIME
I*
LVTTL
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately
13 seconds. When VALTIME is low, the validation
time is approximately 100 ms.
B2, B3, B6, RSVD_GND
—
B7, C8
LVTTL
Reserved—GND.
This pin must be tied to GND for normal operation.
A4–8, B5, B8 RSVD_NC
—
LVTTL
Reserved—No Connect.
This pin must be left unconnected for normal
operation.
C2
VSEL33
I*
D3–D5,
E3–E5
V_DD33
V_DD
D6, D7, E6,
V_DD25
V_DD
E7, F3–F7
LVTTL
Supply
Supply
Select 3.3 V V_DD Supply.
This is an enable pin for the internal regulator. To
enable the regulator, connect this pin to the V_DD33
pins.
3.3 V Supply.
3.3 V power is applied to the V_DD33 pins. Typical
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
2.5 V Supply.
These pins provide a means of connecting the
compensation network for the on-chip regulator.
*Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
Rev. 2.3
27