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PC7410 Datasheet, PDF (6/57 Pages) ATMEL Corporation – PowerPC 7410 RISC Microprocessor Product Specification | |||
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PC7410
â Supports FXU, FPU, and AltiVec load/store traffic
â Complete support for all four architecture AltiVec DST streams
⢠Level 1 (L1) Cache Structure
â 32K 32-byte line, 8-way set associative instruction cache (iL1)
â 32K 32-byte line, 8-way set associative data cache (dL1)
â Single-cycle cache access
â Pseudo Least-recently-used (LRU) replacement
â Data cache supports AltiVec LRU and transient instructions algorithm
â Copy-back or write-through data cache (on a page-per-page basis)
â Supports all PowerPC memory coherency modes
â Non-blocking instruction and data cache
â Separate copy of data cache tags for efficient snooping
â No snooping of instruction cache except for ICBI instruction
⢠Level 2 (L2) Cache Interface
â Internal L2 cache controller and tags; external data SRAMs
â 512K, 1M and 2-Mbyte 2-way set associative L2 cache support
â Copyback or write-through data cache (on a page basis or for all L2)
â 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size
â Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register-
register) late-write synchronous burst SRAMs
â Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM (either all, half or
none of L2 SRAM must be configured as direct mapped
â Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
â 64-bit data bus which also support 32-bits bus mode
â Selectable interface voltages of 1.8V and 2.5V
⢠Memory Management Unit
â 128 entry, 2-way set associative instruction TLB
â 128 entry, 2-way set associative data TLB
â Hardware reload for TLBs
â Four instruction BATs and four data BATs
â Virtual memory support for up to four petabytes (252) of virtual memory
â Real memory support for up to four gigabytes (232) of physical memory
â Snooped and invalidated for TLBI instructions
⢠Efficient Data Flow
â All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are 128 bits wide
â dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF
â L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
â Up to eight outstanding out-of-order cache misses between dL1 and L2/bus
â Up to seven outstanding out-of-order transactions on the bus
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0832FâHIRELâ02/07
e2v semiconductors SAS 2007
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