WCMA2008U1B Datasheet, PDF (5/11 Pages) List of Unclassifed Manufacturers – 256K x 8 Static RAM

WCMA2008U1B
Switching Characteristics Over the Operating Range^[5]
WCMA2008U1B-70
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t_RC
Read Cycle Time
70
ns
t_AA
Address to Data Valid
70
ns
t_OHA
Data Hold from Address Change
10
ns
t_ACE
CE₁ LOW and CE₂ HIGH to Data Valid
70
ns
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Data Valid
OE LOW to Low Z^[6]
OE HIGH to High Z^{[6, 7]}
CE ₁ LOW and CE₂ HIGH to Low Z^[6]
CE ₁ HIGH or CE₂ LOW to High Z^{[6, 7]}
35
ns
5
ns
25
ns
10
ns
25
ns
t_PU
CE₁ LOW and CE₂ HIGH to Power-Up
0
ns
t_PD
WRITE CYCLE^[8,]
CE₁ HIGH or CE₂ LOW to Power-Down
70
ns
t_WC
Write Cycle Time
70
ns
t_SCE
CE₁ LOW and CE₂ HIGH to Write End
60
ns
t_AW
Address Set-Up to Write End
60
ns
t_HA
Address Hold from Write End
0
ns
t_SA
Address Set-Up to Write Start
0
ns
t_PWE
WE Pulse Width
50
ns
t_SD
Data Set-Up to Write End
30
ns
t_HD
t_HZWE
t_LZWE
Data Hold from Write End
WE LOW to High Z^{[6, 7]}
WE HIGH to Low Z^[6]
0
ns
25
ns
10
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V_CC(typ.)/2, input pulse levels of 0 to V_CC(typ.), and output loading
of the specified I_OL /I_OH and 30 pF load capacitance.
6. At any given temperature and voltage condition, t_HZCE is less than t _LZCE, t _HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
7. t_HZOE, t _HZCE, and t _HZWE transitions are measured when the outputs enter a high impedance state.
8. The internal write time of the memory is defined by the overlap of WE, CE₁ = V_IL , and CE₂ = V_IH . All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write.
5