WCMA2008U1B Datasheet, PDF (1/11 Pages) List of Unclassifed Manufacturers – 256K x 8 Static RAM

WCMA2008U1B
WCMA2008U1B
Features
• High Speed
— 70ns availability
• Voltage range
— 2.7V–3.3V
• Ultra low active power
— Typical active current: 1 mA @ f = 1MHz
— Typical active current: 7 mA @ f = f_max (70ns speed)
• Low standby power
• Easy memory expansion withCE₁,CE₂,and OEfeatures
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMA2008U1B is a high-performance CMOS static
RAM organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is device is ideal for portable applications. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
256K x 8 Static RAM
reduces power consumption by 80% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE₁
HIGH or CE₂ LOW).
Writing to the device is accomplished by taking Chip Enable
(CE₁) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE ₂) HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is
then written into the location specified on the address pins (A₀
through A₁₇).
Reading from the device is accomplished by taking Chip En-
able (CE₁) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable 2 (CE₂) HIGH. Under these
conditions, the contents of the memory location specified by
the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW and CE₂ HIGH and WE
LOW).
The WCMA2008U1B is available in a 36-ball FBGA package.
AAA₁₂₀
AA₃₄
AAA₅₆₇
AAAA₁₁₁₈₉₀
CE ₂ ^CE1
WE
OE
Data in Drivers
128K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇