TC5299J Datasheet, PDF (5/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
3.2 Signal Description
PCMCIA Bus Interface Pins
Symbol
Pin #
SA[9:0]
SD[15:8]
SD[7:0]
RST
3-5
7-12,
14
114-117,
119-120,
122-123,
31-29,
27-26,
24-22
16
RSTZ
105
WAIT*
17
REG*
19
IOR*
126
IOW*
2
OE*
127
WE*
34
INPACK*
18
IO16*
21
INT*
125
(RDY/BSY*)
CE1*
35
I/O Description
I The address signal lines of PCMCIA Bus are used to select a
register to be read or written and attribute memory enabled.
I/O Register Access, with DMA inactive, SD0-SD7 are used to
read/write register data. SD8-SD15 invalid during this state.
Remote DMA Bus Cycle, SD0-SD15 contain packet data.
Direction of transfer depends on Remote read/write.
I/O RST is active high and places the TC5299J in a reset mode
immediately. During falling edge the TC5299J controller loads
the configuration from JMP0 – JMP8.
O RSTZ is an active low signal. It is an inverted signal of RST.
O This pin is set low to insert wait states during Remote DMA
transfer.
I REG is an active low input used to determine whether a host
access is to Attribute memory or to common memory. If REG is
low the access is to attribute memory, if REG* is high the access
is to common memory. REG* is also asserted low for all accesses
to the TC5299J IO Registers.
I Read Strobe: Strobe from host to read registers or Remote DMA
read.
I Write Strobe: Strobe from host to read registers or Remote DMA
write.
I Host memory read strobe, when OE* and REG* both low the
attribute memory can be read. When OE* is low and REG* is
high common memory can be read.
I Host memory write strobe, After Power reset if TC5299J is
configured to memory write enable, then WE and REG* is both
low, Attribute memory can be written. When WE is low and
REG* is high common memory can be written.
O An active low signal. Asserted if the host access register or
Remote DMA read cycle.
O IO16* is driven by TC5299J to support host 16 bits access cycle.
O While the TC5299J is configured as a memory device, this pin
servers as RDY/BSY* pin, If the TC5299J is ready to perform a
transfer, this pin is set high. When TC5299J is operated at I/O
mode, this pin is used as an interrupt pin. It indicates that the
TC5299J needs host service. RDY/BSY* state can be read from
the pin Replacement Register (CCR2). While LAN and MODEM
both functions are enabled and IntSel bit in control Register
(CCR5) is zero. This pin output is logical OR of LAN and
MODEM interrupt.
I Card enable 1, is active low signals driven by the host. This
signal provides a card select based on the address decode (decode
by the host).
-5-
Ver. 0.1
07/04/01