TC5299J Datasheet, PDF (22/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
DFR DIS PHY MPA
FO
FAE CRC PRX
Bit
Symbol
D0
PRX
D1
CRC
D2
FAE
D3
FO
D4
MPA
D5
PHY
D6
DIS
D7
DFR
Description
Packet Received Intact: Indicates packet received without error. (Bits CRC, FAE,
FO and MPA are zero for the received packet.)
CRC Error: Indicates packet received with CRC error. Increments Tally Counter
(CNTR1). This bit will also be set for Frame Alignment errors.
Frame Alignment Error: Indicates that the incoming packet did not end on a byte
boundary and the CRC did not match at last byte boundary. Increments Tally
counter (CNTR0).
FIFO Overrun: This bit is set when the FIFO is not serviced causing overflow
during reception. Reception of the packet will be aborted.
Missed Packet: Set when packet intended for node cannot be accepted by TC5299J
because of a lack of receive buffers of if the controller is in monitor mode and did
not buffer the packet to memory. Increments Tally Counter (CNTR2).
Physical/Multicast Address: Indicates whether received packet had a physical or
multicast address type
0: Physical Address Match
1: Multicast/Broadcast Address Match
Receiver Disabled: Set when receiver disabled by entering Monitor mode. Reset
when receiver is re-enabled when exiting Monitor mode.
Deferring: Set when CRS or COL inputs are active. If the transceiver has asserted
the CD line as a result of the jabber, this bit will stay set indicating the jabber
condition.
Note: Following coding applies to CRC and FAE bits
FAE CRC
Type of Error
0
0
0
1
1
0
1
1
No error (Good CRC and <6 Dribble Bits)
CRC ERROR
Legal, will not occur
Frame Alignment Error and CRC Error
5.7.7 Interrupt Mask Register (IMR)
0FH(Write)
The interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in
the Interrupt Status Register (ISR). If an interrupt mask bit is set, an interrupt will be issued whenever
the corresponding bit in the ISR is set. If any bit in the IMR is set low, an interrupt will not occur when
the bit in the ISR is set. The IMR powers up all zeroes.
7
6
5
4
3
2
1
0
-
RDCE CNTE OVWE TXEE RXEE PTXE PRXE
Bit
Symbol
D0
PRXE
D1
PTXE
D2
RXEE
D3
TXEE
D4
OVWE
D5
CNTE
Description
Packet Received Interrupt Enable: Enables Interrupt when packet received.
Packet Transmitted Interrupt Enable: Enables Interrupt when packet is transmitted.
Receive Error Interrupt Enable: Enables Interrupt when packet received with error.
Transmit Error Interrupt Enable: Enables Interrupt when packet transmission
results in error.
Over Write Warning Interrupt Enable: Enables Interrupt when Buffer management
Logic lacks sufficient buffers to store incoming packet.
Counter Overflow Interrupt Enable: Enables Interrupt when MSB of one or more
f h N k T ll
hb
-22-
Ver. 0.1
07/04/01