TC5299J Datasheet, PDF (14/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
LCINT
LINK
MIICIM
MIICINT
EXTRMII
LINT
XX
R/W The Link-Changed interrupt report bit.
1: indicates the Link status changed.
R When this bit is high, link test integrity checking is good. Otherwise, indicate link
signal lost.
R/W This bit should be set to 0.
R/W This bit should be set to 0.
R This bit should be set to 0.
R/W LAN interrupt status indicator. To write a one to this bit can reset it.
X Reserved
5.3 Configuration Register C
This register just set in EEPROM and it can’t been read from user.
7
6
5
XX
XX
XX
4
3
FE
RBHI1
2
RBHI0
1
0
RBLO1 RBLO0
Name
RBLO [1:0]
RBHI [1:0]
FE
XX
R/W Description
X This is low value of receive buffer setting on full-duplex flow-control. It means that
are few data in Rx buffer.
00: Less than 1.5K data in Rx buffer.
01: Less than 3k data in Rx buffer.
10: Less than 4.5k data in Rx buffer.
11: Less than 6k data in Rx buffer.
X That is high value of receive buffer setting on full-duplex flow-control. It means that is
few space in Rx buffer.
00: Less than 1.5K space in Rx buffer.
01: Less than 3k space in Rx buffer.
10: Less than 4.5k space in Rx buffer.
11: Less than 6k space in Rx buffer.
X Flow control enable bit in full-duplex mode.
0: Disable flow-control.
1: Enable flow-control.
X Reserved
PS. X: Can’t read, just set these bit in the EEPROM.
5.4 Hardware Configuration
These functions are configured during a power on RESET.
Symbol
JMP0
JMP1
I/O Description
I/O Power on setting:
0: Enter I/O mode (Same as CCR0, bit 5)
I/O Power on setting:
1: Full address decode(A9-A0)
0: Separate address decode(A5-A0)
-14-
Ver. 0.1
07/04/01