MTD505 Datasheet, PDF (5/19 Pages) List of Unclassifed Manufacturers – 5 Port 10M/100M Ethernet Switch

MYSON
TECHNOLOGY
MTD505
(Preliminary)
Name
TXD4_3
TXD4_2
TXD4_0
TXD4_1
COL4
CLK25M
RMII/MII Port Interface Pins
Pin Number
19
20
22
21
18
109
I/O
Descriptions
O Port4 MII transmit data bit_3. In RMII mode, this pin don’t use.
O Port4 MII transmit data bit_2. In RMII mode, this pin don’t use.
O Port4 RMII/MII transmit data bit_0.
O Port4 RMII/MII transmit data bit_1.
I Port4 MII collision input.
In RMII mode, this pin don’t use.
O Port4 MII 25MHz clock output.
Name
AD[8:0]
DQ[31:0]
RASB
CASB
WEB
BA
CS0B
CS1B
MEMCLK
SGRAM/SDRAM Interface Pins
Pin Number I/O
Descriptions
59,60,61,62, ^{O Memory row/column address bus outputs}
65,66,67,68,
69
AD[7:0] are row/column address [7:0].
AD[8] : This pin should connect to SGRAM/SDRAM MSB address bit.
38~42,45~55 I/O Memory data bus
,78~80,
83~95
75
76
77
73
74
70
57
O SGRAM/SDRAM row address select
O SGRAM/SDRAM column address select
O SGRAM/SDRAM write enable
O SGRAM/SDRAM bank select
O Memory chip select 0
O Memory chip select 1
O Memory clock output.
Note: SGRAM/SDRAM access time: 10 ns (max)
Name
LEDDATA
[7:0]
LED Interface Pins
Pin Number I/O
Descriptions
I/O LED data output.
These LED pins report Port0~7 Link/Rx activity status using
LEDCLK1 strobe , and report packet buffer utilization status using
LEDCLK2 strobe.
LEDDATA [0] [1] [2] [3] [4] [5] [6] [7]
100,101,102,
103,104,105,
106,107
LEDCLK1 LR0 LR1 LR2 LR3 LR4 --- --- ---
LEDCLK2 Uti0 Uti1 Uti2 Uti3 Uti4 --- BFull MFail
note:
LRn: means per port’s Link_RxAct status.
Uti0: 5%, Uti1: 10%, Uti2: 20%, Uti3: 35%, Uti4: 50 above .
BFull: Buffer almost full alarm signal.
Mfail: External memory poer on test failure.
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MTD505 Revision 1.2 14/04/2000