MTD505 Datasheet, PDF (14/19 Pages) List of Unclassifed Manufacturers – 5 Port 10M/100M Ethernet Switch

MYSON
TECHNOLOGY
MTD505
(Preliminary)
TABLE 1. MII r egister s
GLOBAL REGISTERS
REG
NO
Bits
15-8
7
Name R/W
Descriptions
StsReg1
bit[12:8] outputs port4-0 TXDMA TPUR(fifoempty),
bit[15:13] : reserved.
RO
STATUS REGISTER 1
0 BufBistDone.
1 BufBistErr.
2 BufInitDone.
3 AddrTblBistDone.
4 AddrTblBistErr.
5 LthTblBistDone.
6 LthTblBistErr.
7 MemBistDone.
8 MemBistErr.
9 EEDone.
10 FreeCntIs0.
15-11 Reserved.
8
CtlReg7 R/W
CONTROL REGISTER 7
7-0
bit[4:0] output mii polling port4-0 flow control informa-
tion, bit[7:5] : reserved
15-8
bit[12:8] output mii polling port4-0 link information,
bit[15:13] : reserved.
"1" means flow control enable or link good.
9
CtlReg8 R/W
CONTROL REGISTER 8
7-0
bit[4:0] output mii polling port4-0 speed information,
bit[7:5] : reserved.
15-8
bit[12:8] output mii polling port4-0 full information,
bit[15:13] :reserved.
"1" means 100M or full duplex.
PORT REGISTERS
1
StsReg1 RO
STATUS REGISTER 1
10-0
bit[10:0] output Port Tx queue head value.
15-11
Reserved.
2
StsReg2 RO
STATUS REGISTER 2
10-0
bit[10:0] output Port Tx queue tail value.
15-11
Reserved.
3
StsReg3 RO
STATUS REGISTER 3
10-0
bit[10:0] output Port Tx queue count value.
15-11
Reserved.
4
CtlReg1 R/W
CONTROL REGISTER 1
7-0
bit[7:0] select Port VLAN group.
15-8
Reserved.
Default
14/19
MTD505 Revision 1.2 14/04/2000