VMX51C900 Datasheet, PDF (41/55 Pages) List of Unclassifed Manufacturers – Versa Mix 8051 MCU with LCD Controller and ADC

VMX51C900
The Watchdog Timer
The VMX51C900 watchdog timer (WDT) is a 16-bit
free-running counter operating from an independent
250KHz internal RC oscillator. An overflow of the WDT
counter will reset the processor.
The WDT is a useful safety measure for systems that
are susceptible to noise, power glitches and other
conditions that could cause the software to go into
infinite dead loops or runaways. The WDT provides the
user software with a recovery mechanism from
abnormal software conditions.
Watchdog Timer Registers
The configuration and use of the VMX51C900
watchdog timer is handled by three registers:
WDTKEY, WDTCTRL and SYSCON.
The WDTKEY register ensures that the watchdog timer
is not inadvertently reset in case of program
malfunction.
The WDTCTRL register is by default configured as a
read-only register. To modify its contents, two
consecutive write operations to the WDTKEY register
must be performed as follows:
MOV WDTKEY,#01Eh
MOV WDTKEY,#0E1h
Once the configuration or WDT reset operation is
complete, the WDTCTRL register can be restored to
read-only by writing the following sequence into the
WDTKEY register:
MOV WDTKEY,#0E1h
MOV WDTKEY,#01Eh
TABLE 51: WATCH DOG TIMER KEY REGISTER: WDTKEY – SFR 97H
7
6
5
43
2
1
0
WDTKEY7:0
Bit
Mnemonic Description
7:0
WDTKEY Watchdog Key
Once the WDT is enabled, the user software must
clear it periodically. If the WDT is not cleared, its
overflow will trigger a reset of the VMX51C900.
TABLE 52: WATCH DOG TIMER REGISTERS: WDTCTRL – SFR 9FH
7
WDTE
6
Unused
5
WDT
CLR
43
Unused
2
WDT
PS2
1
WDT
PS1
0
WDT
PS0
Bit
Mnemonic Description
7
WDTE
Watchdog Timer Enable Bit
6
Unused
-
5
WDTCLR Watchdog Timer Counter Clear Bit
[4:3]
Unused
-
2
WDTPS2
Clock Source Divider Bit 2
1
WDTPS1
Clock Source Divider Bit 1
0
WDTPS0
Clock Source Divider Bit 0
The WDT timeout delay can be adjusted by configuring
the clock divider input for the WDT time base source
clock. To select the divider value, the
[WDTPS2~WDTPS0] bits of the watchdog timer
control register should be set accordingly.
The following table indicates the approximate timeout
periods for different values of the WDTPSx bits of the
watchdog timer register.
TABLE 53: TIMEOUT PERIOD AT
WDTPS [2:0]
WDT Period
000
2.048ms
001
4.096ms
010
8.192ms
011
16.384ms
100
32.768ms
101
65.536ms
110
131.072ms
111
262.144ms
To enable the WDT, bit 7 (WDTE) of the WDTCTRL
register must be set to 1. The 16-bit counter will then
begin counting from the 250KHz oscillator divided,
according to the value of the WDTPS2~WDTPS0 bits.
The WDT is cleared by setting the WDTCLR bit of the
WDTCTRL to 1. This will clear the contents of the 16-
bit counter and force it to restart.
If the WDT overflows, the processor will be reset, the
WDR bit (7) of the SYSCON register will be set to 1
and the WDTE bit will be cleared to 0. The user should
check the WDR bit if an unexpected reset has taken
place.
______________________________________________________________________________________________
www.ramtron.com
page 41 of 55