SD1210 Datasheet, PDF (41/46 Pages) List of Unclassifed Manufacturers – Dual-Interface SXGA TFT LCD Display Controller

SmartASIC, Inc.
SD1210
Non_full_screen
Divisor_value
IQ_value
Panel_on
1 RW 66H[0] Indicates when input data is non full screen. Can be
clear by cpu
11
R 67H[2:0], Read only register containing value of clock frequency
68H when divisor_valid is asserted
30
R 69H[5:0], Read only register containing value of image quality
6AH,6BH, when either ics_iq_valid or iq_valid is asserted
6CH
1 RW 6DH[0] 1: turn on all the outputs to the panel
0: disable outputs to the panel (need to disable
EEPROM 265H[3], 266H[7], 266H[3], 267H[7],
267H[3] to get complete output disable).
ICS_hsize_value 11
R 6EH[2:0], Read only register containing value of hsize when
6FH ics_hsize_valid is asserted
Rom_clk_sel
6 RW 70H[5:0] Divisor value use to divide fast pwm_free_clk to
slower free_clk
3.7. Control Flow
When SD1210 is powered up, the reference system and SD1210 will perform the
following functions in sequence:
1. System will generate a Power-On Reset to SD1210.
2. Once the SD1210 receives the Reset, SD1210 will load the contents of EEPROM
and start the auto-calibration process.
3. In the meantime, the external CPU can change the contents of the control registers
of the SD1210. If necessary, the external CPU can send an additional Reset to
restart the whole process.
November, 1999
SmartASIC Confidential
41
Revision B