English
Language : 

SD1210 Datasheet, PDF (32/46 Pages) List of Unclassifed Manufacturers – Dual-Interface SXGA TFT LCD Display Controller
SmartASIC, Inc.
SD1210
Gamma_offset3_g
8
2A8H Gamma_offset3 for green
Gamma_offset4_g
8
2A9H Gamma_offset4 for green
Gamma_offset5_g
8
2AAH Gamma_offset5 for green
Gamma_offset6_g
8
2ABH Gamma_offset6 for green
Gamma_offset7_g
8
2ACH Gamma_offset7 for green
Gamma_offset0_b
8
2ADH Gamma_offset0 for blue
Gamma_offset1_b
8
2AEH Gamma_offset1 for blue
Gamma_offset2_b
8
2AFH Gamma_offset2 for blue
Gamma_offset3_b
8
2B0H Gamma_offset3 for blue
Gamma_offset4_b
8
2B1H Gamma_offset4 for blue
Gamma_offset5_b
8
2B2H Gamma_offset5 for blue
Gamma_offset6_b
8
2B3H Gamma_offset6 for blue
Gamma_offset7_b
8
2B4H Gamma_offset7 for blue
Check sum
8
2B5H Sum of all part 9 bytes (keep only lower 8 bit)
3.6. CPU interface
The SD1210 supports a 2-wire serial interface to an external CPU. The interface
allows the external CPU to access and modify control registers inside the SD1210.
The 2-wire serial interface is similar to the EEPROM interface, and the CPU is the
host that drives the SCL all the time as the clock and for “start” and “stop” bits. The
SCL frequency can be as high as 5MHz. The SDA is a bi-directional data wire. This
interface supports random and sequential write operations for the CPU to modify one
or multiple control registers, and random and sequential read operations for the CPU
to read all or part of the control registers.
The default device ID for the SD1210 is fixed “1111111”. The device ID can be
programmed through EEPROM entry 200H bit 0 through bit 6. This avoids any
conflict with other 2-wire serial devices on the same bus.
The following table briefly describes the SD1210 control registers. The external CPU
can read these registers to know the state of the SD1210 as well as the result of input
mode detection and phase calibration. The external CPU can modify these control
registers to disable several SD1210 features and force the SD1210 into a particular
state. When the CPU modifies the control registers, the new data will be first stored in
a set of shadow registers, and then copied into the actual control registers when the
“CPU Control Enable” bit is set. When the “CPU Control Enable” bit is set, the
external CPU will retain control and the SD1210 will not perform the auto mode
detection and auto calibration.
The external CPU is able to adjust the size of the output image and move the output
image up and down by simply changing the porch size and pixel and line numbers of
the input signal. These adjustments can be tied to the external user control button on
the monitor.
November, 1999
SmartASIC Confidential
32
Revision B