SD1210 Datasheet, PDF (27/46 Pages) List of Unclassifed Manufacturers – Dual-Interface SXGA TFT LCD Display Controller

SmartASIC, Inc.
SD1210
[7:0]
Mode 832x624
Sync Polarity
Res5 threshold
[10:8]
Res5 threshold
[7:0]
Mode 1024x768
Sync Polarity
Res6 threshold
[10:8]
Res6 threshold
[7:0]
Mode 1152x864
Sync Polarity
Res7 threshold
[10:8]
Res7 threshold
[7:0]
Mode 1152x870
Sync Polarity
Res8 threshold
[10:8]
Res8 threshold
[7:0]
Mode 1280x960
Sync Polarity
Res9 threshold
[10:8]
Res9 threshold
[7:0]
Mode 1280x1024
Sync Polarity
Res10 threshold
[10:8]
Res10 threshold
[7:0]
Reserve mode 1
Sync Polarity
Reserve mode 1
Res threshold [10:8]
Reserve mode 1
Res threshold [7:0]
Reserve mode 2
Sync Polarity
Reserve mode 2
Res threshold [10:8]
Reserve mode 2
Res threshold [7:0]
Reserve mode 3
Sync Polarity
Reserve mode 3
Res threshold [10:8]
November, 1999
Revision B
lower bound for 832x624
2
20DH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
20DH[2:0] Upper bound of the line number for 832x624 mode
8
20EH Upper bound of the line number for 832x624 mode, and
lower bound for 1024x768
2
20FH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
20FH[2:0] Upper bound of the line number for 1024x768 mode
8
210H Upper bound of the line number for 1024x768 mode, and
lower bound for 1152x864
2
211H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
211H[2:0] Upper bound of the line number for 1152x864 mode.
8
212H Upper bound of the line number for 1152x864 mode, and
lower bound for 1152x870
2
213H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
213H[2:0] Upper bound of the line number for 1152x870 mode.
8
214H Upper bound of the line number for 1152x870 mode, and
lower bound for 1280x960.
2
215H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
215H[2:0] Upper bound of the line number for 1280x960 mode.
8
216H Upper bound of the line number for 1280x960 mode, and
lower bound for 1280x1024.
2
217H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
217H[2:0] Upper bound of the line number for 1280x1024 mode.
8
218H Upper bound of the line number for 1280x1024 mode.
2
219H[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
219H[2:0] Resolution threshold for reserve mode 1
8
21AH Resolution threshold for reserve mode 1
2
21BH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
21BH[2:0] Resolution threshold for reserve mode 2
8
21CH Resolution threshold for reserve mode 2
2
21DH[5:4] The polarity of input synchronization signals.
Bit 0 is for VSYNC and bit 1 is for HSYNC
3
21DH[2:0] Resolution threshold for reserve mode 3
SmartASIC Confidential
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