VS1011E Datasheet, PDF (36/49 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
VS1011e
VS1011E
9. OPERATION
9 Operation
9.1 Clocking
VS1011e operates on a single, nominally 24.576 MHz fundamental frequency master clock. This clock
can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface
(pins XTALI and XTALO). Also, 12.288 MHz external clock can be internally clock-doubled to 24.576
MHz. This clock is sufficient to support a high quality audio output for all codecs, sample rates and
bitrates, with bass and treble enhancers.
9.2 Hardware Reset
When the XRESET -signal is driven low, VS1011e is reset and all the control registers and internal states
are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1011e are in minimum
power consumption stage, and where clocks are stopped. Also XTALO and XTALI are grounded.
After a hardware reset (or at power-up), the user should set such basic software registers as SCI VOL
for volume (and SCI CLOCKF if the input clock is anything else than 24.576 MHz) before starting
decoding.
9.3 Software Reset
In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register
(Chapter 8.6.1). Then wait for at least 2 µs, then look at DREQ. DREQ will stay down for at least 6000
clock cycles, which means an approximate 250 µs delay if VS1011e is run at 24.576 MHz. After DREQ
is up, you may continue playback as usual.
If you want to make sure VS1011e doesn’t cut the ending of low-bitrate data streams and you want to do
a software reset, it is recommended to feed 2048 zeros to the SDI bus after the file and before the reset.
Version 1.04, 2007-10-08
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