VS1011E Datasheet, PDF (17/49 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
VS1011e
VS1011E
7. SPI BUSES
7 SPI Buses
7.1 General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1011e’s
Serial Data Interface SDI (Chapters 7.3 and 8.4) and Serial Control Interface SCI (Chapters 7.5 and 8.5).
7.2 SPI Bus Pin Descriptions
7.2.1 VS1002 Native Modes (New Mode)
These modes are active on VS1011e when SM SDINEW is set to 1. DCLK and SDATA are not used for
data transfer and they can be used as general-purpose I/O pins (GPIO2 and GPIO3). BSYNC function
changes to data interface chip select (XDCS).
SDI Pin SCI Pin
XDCS XCS
SCK
SI
-
SO
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. If SM SDISHARE is 1, pin
XDCS is not used, but the signal is generated internally by inverting
XCS.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. If a chip select is active, SI is sampled on the rising CLK edge.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
7.2.2 VS1001 Compatibility Mode
This mode is active when SM SDINEW is 0 (default). In this mode, DCLK, SDATA and BSYNC are
active.
Version 1.04, 2007-10-08
17