VS1011E Datasheet, PDF (19/49 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
VS1011e
VS1011E
7. SPI BUSES
BSYNC
SDATA
DCLK
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5: BSYNC Signal - one byte transfer.
order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiver
stays active and next 8 bits are also received.
BSYNC
SDATA
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DCLK
Figure 6: BSYNC Signal - two byte transfer.
Using VS1001 compatibility mode in new designs is strongly discouraged.
7.4 Data Request Pin DREQ
The DREQ pin/signal is used to signal if VS1011e’s FIFO is capable of receiving data. If DREQ is high,
VS1011e can take at least 32 bytes of SDI data or one SCI command. When these criteria are not met,
DREQ is turned low, and the sender should stop transferring new data.
Because of a 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without
checking the status of DREQ, making controlling VS1011e easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It should not abort a transmission that has already
started.
Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1011e DREQ is also used
to tell the status of SCI.
7.5 Serial Protocol for Serial Command Interface (SCI)
7.5.1 General
The serial bus protocol for the Serial Command Interface SCI (Chapter 8.5) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising clock edge, so the user should update data at the falling clock
edge. Bytes are always sent MSb firrst.
Version 1.04, 2007-10-08
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