VS1011E Datasheet, PDF (32/49 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
VS1011e
VS1011E
8. FUNCTIONAL DESCRIPTION
8.6.3 SCI BASS (RW)
Name
ST AMPLITUDE
ST FREQLIMIT
SB AMPLITUDE
SB FREQLIMIT
Bits
15:12
11:8
7:4
3:0
Description
Treble Control in 1.5 dB steps (-8..7, 0 = off)
Lower limit frequency in 1000 Hz steps (0..15)
Bass Enhancement in 1 dB steps (0..15, 0 = off)
Lower limit frequency in 10 Hz steps (2..15)
The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most out
of the users earphones without causing clipping.
VSBE is activated when SB AMPLITUDE is non-zero. SB AMPLITUDE should be set to the user’s
preferences, and SB FREQLIMIT to roughly 1.5 times the lowest frequency the user’s audio system can
reproduce. For example setting SCI BASS to 0x00f6 will have 15 dB enhancement below 60 Hz.
Note: Because VSBE tries to avoid clipping, it gives the best bass boost with dynamical music material,
or when the playback volume is not set to maximum. It also does not create bass: the source material
must have some bass to begin with.
Treble Control VSTC is activated when ST AMPLITUDE is non-zero. For example setting SCI BASS
to 0x7a00 will have 10.5 dB treble enhancement at and above 10 kHz.
Bass Enhancer uses about 2.1 MIPS and Treble Control 1.2 MIPS at 44100 Hz sample rate. Both can be
on simultaneously.
8.6.4 SCI CLOCKF (RW)
SCI CLOCKF is used to tell if the input clock XTALI is running at something else than 24.576 MHz.
XTALI
is
set
in
2
kHz
steps.
Thus,
the
formula
for
calculating
the
correct
value
for
this
register
is
XT ALI
2000
(XTALI is in Hz). Values may be between 0..32767, although hardware limits the highest allowed speed.
Also, with speeds lower than 24.576 MHz all sample rates are no longer available. For example with
24 MHz clock 48 kHz is played 2.5% off-key.
Setting the MSB of SCI CLOCKF to 1 activates internal clock-doubling when the sample rate is next
configured.
Note: SCI CLOCKF must be set before beginning decoding audio data; otherwise the sample rate will
not be set correctly.
Example
1:
For
a
26
MHz
clock
the
value
would
be
26000000
2000
=
13000.
Example 2: For a 13 MHz external clock and using internal clock-doubling for a 26 MHz internal
frequency,
the
value
would
be
0x8000
+
13000000
2000
=
39268.
Example
3:
For
a
24.576
MHz
clock
the
value would
be
either
24576000
2000
=
12288,
or
just
the
default
value 0. For this clock frequency, SCI CLOCKF doesn’t need to be set.
Version 1.04, 2007-10-08
32