FDC37N958FR Datasheet, PDF (273/316 Pages) List of Unclassifed Manufacturers – Notebook I/O Controller with Enhanced Keyboard and System Control

Control
Shadow
Register
OPEN MODE
INDEX ADDRESS
SYSTEM
R/W
8051
ADDRESS
(7F00 +)
8051
R/W
POWER
SOURCE
VCC1
POR
VCC2
POR
ZERO
WAIT
STATE
(1)
NOTES
SEE
PAGE
#
Notes:
1. When accessed for a read or write by the system, the registers marked with a “Y” will drive the
zero wait state pin active.
2. Interrupt is cleared when read by the 8051.
3. Interrupt is cleared when read by the host.
4. When IRESET_OUT is cleared (written from “1” to”0”) 8051STP_CLK bit D0 as well as HMEM bits
D1 and D0 are all set to “1”.
5. These registers are reset 500"s to 1ms following the condition that BOTH VCC2 is valid and
PWRGD is asserted given that the RTC is in normal mode and the VRT bit is set (refer to the RTC
section). If the RTC is not in normal mode and/or the VRT bit is not set then these registers are
reset within 10"s following the condition that BOTH VCC2 is valid and PWRGD is asserted.
System Shadow Registers
The FDC37N958FR makes the following Control
Registers readable by supplying a set of Index
8051
Sys. Sys ^{address 8051}
index R/W ^{(7F00+) R/W}
Force
IDX99 R
------ N/A
Diskchange
Floppy Data IDX9 R
------ N/A
Rate Select A
Shadow
Register
UART1 FIFO IDX9 R
------ N/A
Control
B
Shadow
Register
UART2 FIFO IDX9 R
------ N/A
Control
C
Shadow
Register
Registers accessable either through Logical
Device 7 when in Confuration State or through
the Open Mode Index and Data registers when
in Run State.
Power _VCC1
Source _POR
VCC2
POR
Zero
Wait
State (9)
Notes
VCC2
03h
------
VCC2
N/A
------
VCC2
00h
VCC2
00h
SMSC DS – FDC37N958FR
Page 267
Rev. 09/01/99