FDC37N958FR Datasheet, PDF (200/316 Pages) List of Unclassifed Manufacturers – Notebook I/O Controller with Enhanced Keyboard and System Control

Operation Registers
The 8051 uses the following three memory
mapped registers to gain access to and control
the parallel port interface.
PARALLEL PORT STATUS Register
Host
N/A
8051
0x7F3A
Power
VCC2
Default
0x00
D7
D6 D5 D4
D3
D2 D1
D0
8051
R
R
R
R
R
R
R
R/W
R/W
System
N/A
N/A N/A N/A N/A N/A N/A
N/A
R/W
Bit Def nBUSY nACK PE SLCT nERR 0
0 PP_HA
1 = Host (or FDC)
controls the
Parallel Port
Interface.
0 = 8051 controls
the Parallel Port
Interface (default).
If 8051 access to the parallel port pins is enabled; The level of the parallel port status pins can be read
by reading this register.
Bit D7 (nBUSY): reflects the inverse state of pin BUSY
Bit D6 (nACK): reflects the current state of pin nACK
Bit D5 (PE):
reflects the current state of pin PE
Bit D4 (SLCT): represents the current state of pin SLCT
Bit D3 (nERR): reflects the current state of pin nERR
SMSC DS – FDC37N958FR
Page 194
Rev. 09/01/99