Si5321 Datasheet, PDF (26/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321
Table 10. Si5321 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
H5
FRQSEL[0]
I*
H8
FRQSEL[1]
B3
FRQSEL[2]
LVTTL*
Clock Output Frequency Range Select.
Select the frequency range of the clock output, CLK-
OUT. (See Table 3 on page 7.)
001 = 19 MHz Frequency Range.
000 = 39 MHz Frequency Range.
100 = 78 MHz Frequency Range.
010 = 155 MHz Frequency Range.
101 = 311 MHz Frequency Range.
011 = 622 MHz Frequency Range.
110 = 1.25 GHz Frequency Range.
111 = 2.5 GHz Frequency Range.
A3
FEC[0]
I*
LVTTL*
FEC Selection.
A2
FEC[1]
Enables or disables scaling of the input-to-output
B2
FEC[2]
frequency multiplication factor for FEC clock rate
compatibility.
The frequency of the CLKOUT output is a multiple of
the frequency of the CLKIN input. Selecting the
clock input range, the clock output range, and the
FEC scaling factor sets the input-to-output fre-
quency multiplication factor. The clock output fre-
quency is selected using the FRQSEL[2:0] pins. The
clock input frequency is selected using the
INFRQSEL[2:0] pins. Scaling factors of 255/238,
238/255, 255/237, 237/255, 66/64, or 64/66 may be
selected for FEC operation using the FEC[2:0] con-
trol pins as indicated below. Scaling factors of 255/
237, 237/255, 66/64, or 64/66 require that the input
clock rate be in the 155 MHz or higher range.
000 = No FEC scaling.
001 = 255/238 FEC scaling.
010 = 238/255 FEC scaling.
011 = Reserved.
100 = 255/237 FEC scaling (155 MHz or higher
input clock range required).
101 = 237/255 FEC scaling (155 MHz or higher
input clock range required).
110 = 66/64 FEC scaling (155 MHz or higher input
clock range required).
111 = 64/66 FEC scaling (155 MHz or higher input
clock range required).
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
26
Rev. 2.3