Si5321 Datasheet, PDF (25/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321
Table 10. Si5321 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
D1
CLKIN+
I
AC Coupled System Clock Input.
E1
CLKIN–
200–500 mV_{PPD Clock input to the DSPLL circuitry. The frequency of}
(See Table 2) _{the CLKIN signal is multiplied by the DSPLL to gen-}
erate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The
frequency of the CLKIN clock input can be in the 19,
38, 77, 155, 311, or 622 MHz range (nominally
19.44, 38.88, 77.76, 155.52, 311.04, or
622.08 MHz) as indicated in Table 3 on page 7. The
clock input frequency is selected using the
INFRQSEL[2:0] pins. The clock output frequency is
selected using the FRQSEL[1:0] pins. An additional
scaling factor may be selected for FEC operation
using the FEC[2:0] control pins.
F1
INFRQSEL[0]
I*
G1
INFRQSEL[1]
H1
INFRQSEL[2]
LVTTL*
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 38 MHz range.
011 = 77 MHz range.
100 = 155 MHz range.
101 = 311 MHz range.
110 = 622 MHz range.
111 = Reserved.
H6
CLKOUT+
O
H7
CLKOUT–
CML
Differential Clock Output.
High-frequency clock output. The frequency of the
CLKOUT output is a multiple of the frequency of the
CLKIN input. The input-to-output frequency multipli-
cation factor is set by selecting the clock input range
and the clock output range. The frequency of the
CLKOUT clock output can be in the 19, 38, 77, 155,
311, 622, 1244 or 2488 MHz range as indicated in
Table 3 on page 7. The clock output frequency is
selected using the FRQSEL[2:0] pins. The clock
input frequency is selected using the
INFRQSEL[2:0] pins. An additional scaling factor
may be selected for FEC operation using the
FEC[2:0] control pins.
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
Rev. 2.3
25