SA25C020 Datasheet, PDF (24/31 Pages) List of Unclassifed Manufacturers – 2Mb EEPROM with 25MHz SPI Bus Interface

Byte or Page Write (PW)
The Byte or Page Write instruction allows
bytes to be programmed and erased in the
memory (changing bits from 1 to 0 and
from 0 to 1). In order to program to the
SA25C020, two separate instructions must
be executed. The device must first be write
enabled via the WREN instruction, and
then a Byte or Page Write sequence
(which consists of four bytes plus data)
may be executed. The address of the
memory locations to be written must be
outside the protected address field location
selected by the Block Write Protection
level. During an internal Write cycle, all
commands are ignored except the RDSR
instruction.
A Byte or Page Write instruction requires
the following sequence:
After the CSb line is pulled
low to select the device, the
WRITE opcode is transmitted
via the SI line, followed by the
byte address and the data
(D7-D0) to be written.
Programming starts after the CSb pin is
brought high. The CSb pin's low-to-high
transition must occur during the SCK low
time, immediately after the clock in the D0
(LSB) data bit. The instruction sequence is
shown in Figure 15, page 25.
SA25C020 Advanced Information
SAIFUN
24
As soon as CSb is driven high, the
self-timed Write cycle (whose duration is
defined as T_PW) is initiated. While the Page
Write cycle is in progress, the status
register may be read to check the value of
the Write in Progress (/RDY) bit. The /RDY
bit is 1 during the self-timed Page Write
cycle, and 0 when it is completed. The
Write Enable Latch (WEN) bit is reset at
some unspecified time before the cycle is
completed.
The SA25C020's PW operation is capable
of up to a 256-byte writing, from 1 to 256
bytes at a time (changing bits from 1 to 0
and from 0 to 1), provided that they lie in
consecutive addresses on the same page
of memory. After each byte is received, the
eight low-order address bits are internally
incremented by one. If more than 256
bytes of data are transmitted, the address
counter rolls over and the previously
written data is overwritten. The SA25C020
is automatically returned to the write
disable state at the completion of a Write
cycle.
NOTES:
1. If the device is not write enabled,
the device ignores the PW
instruction and returns to the
standby state when CSb is brought
high. A new CSb falling edge is
required to re-initiate the serial
communication.
2. A PW instruction applied to a page
that is protected by the Block
Protect (BP1, BP0) bits (as
described in Table 7, page 18, and
Table 8, page 21) is not executed.