SA25C020 Datasheet, PDF (18/31 Pages) List of Unclassifed Manufacturers – 2Mb EEPROM with 25MHz SPI Bus Interface

Read Status Register (RDSR)
The RDSR instruction provides read
access to the status register. The
BUSY/RDY and WREN statuses of the
device can also be determined by this
instruction. In addition, the Block Write
Protection bits indicate the extent of
protection employed. In order to determine
the status of the device, the value of the
/RDY bit can be continuously polled before
sending any write instruction.
Table 7. Read Status Register Definition
Bit
Definition
Bit 0 (/RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bit 7
(WPBEN)
Bit 0 = 0 (/RDY) indicates that the
device is READY.
Bit 0 = 1 indicates that a write
cycle is in progress.
Bit 1 = 0 indicates that the device
is not write enabled.
Bit 1 = 1 indicates that the device
is write enabled.
Block Write Protect Bit 0
Block Write Protect Bit 1
Write Protect Mode Enable Bit
SA25C020 Advanced Information
SAIFUN
18
Bit 7 (WPBEN) is Hardware Write Protect
mode. If this bit is a 1, this mode is enabled
and the status register is write protected.
Bits 6 through 4 are always 0.
Bit 3 (BP1) and Bit 2 (BP0) together
indicate a Block Write Protection previously
sent to the device.
Bits 0 and 1 are 1 during an internal write
cycle.
Bit 1 (WEN) indicates the Write Enable
status of the device. This bit is read by
executing an RDSR instruction. If this bit is
1, the device is write enabled; if it is 0, it is
write disabled.
Bit 0 (/RDY) indicates the Busy/Ready
status of the device. This bit is a read-only
bit and is read by executing an RDSR
instruction. If this bit is 1, the device is busy
doing a Program or Erase cycle; if it is 0,
the device is ready.