SA25C020 Datasheet, PDF (17/31 Pages) List of Unclassifed Manufacturers – 2Mb EEPROM with 25MHz SPI Bus Interface

Functional Description
Instructions
Figure 9 presents a schematic diagram of
the SA25C020 's SPI serial interface.
MASTER:
MICROCONTROLLER
DATA OUT
DATA IN
SERIAL CLOCK
SSO
SS1
SS2
SS3
SLAVE
SA25C020
SI
SO
SCK
CSb
SI
SO
SCK
CSb
SI
SO
SCK
CSb
SI
SO
SCK
CSb
Figure 9. SPI Serial Interface
SA25C020 Advanced Information
SAIFUN
17
The SA25C020 's SPI consists of an 8-bit
instruction register that decodes a specific
instruction to be executed. Thirteen
different instructions (called opcodes) are
incorporated in the device for various
operations. Table 5 lists the instruction set
and the format for proper operation. All
opcodes, array addresses and data are
transferred in an MSB-first-LSB-last
fashion. Detailed information about each of
these opcodes is provided for the individual
instruction descriptions in the sections that
follow.
Table 5. Instruction Set
Instruction
Name
Instruction
Format
Operation
WREN
WRDI
RDSR
WRSR
READ
Byte or Page
Write
READ_ID
0000 0110
Set Write Enable
Latch
0000 0100
Reset Write Enable
Latch
0000 0101
Read Status
Register
0000 0001
Write Status
Register
0000 0011
Read Data from
Memory Array
0000 0010
Write Data to
Memory Array
1010 1011
+3 dummy bytes
Read ID
In addition to the instruction register, the
device also contains an 8-bit status register
that can be accessed by RDSR and WRSR
instructions. The byte defines the Block
Write Protection (BP1 and BP0) levels,
Write Enable (WEN) status, Busy/Rdy
(/RDY) status and Hardware Write Protect
(WPBEN) status of the device. Table 6
illustrates the format of the status register.
Table 6. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
WPBEN X X X BP1 BP0 WEN /RDY