TIGER560 Datasheet, PDF (17/37 Pages) List of Unclassifed Manufacturers – USB Controller for Low Cost VoIP solutions

Tiger560
Advance Information
Serial Port Interface
The Tiger560 serial port consists of one data clock (DCLK), one frame synchronization clock
(FSC) and two data lines (DIN and DOUT).
DCLK and FSC can either be inputs or outputs to the Tiger560. DCLK can either be the same as
the data rate or twice the data rate. If DCLK is the same as the data rate the internal clock
doubler should be turned on for correct operation.
The serial port interface is controlled by two sets of registers based on the Tiger560 chip mode
selection.
If Tiger560 is set to use original Tiger500 USB descriptor mode(HA[3:2]==2’b00), the serial port
interface is controlled by the same set of registers as Tiger500. If Tiger560 is set to use the
Tiger560 USB descriptor (HA[3:2]==2’b01) and the audio class device is enabled
(productID[15:14] == 2’b01 or 2’b10), the serial port interface is controlled by productID definition
and a set of registers that is specific to the Tiger560. For detailed register definition please see
the registers section.
Tiger500 mode: Serial port signals
The FSC input should be an 8 KHz clock. Within one FSC period, the first 32 bits of data are
transmitted and received. The data is clocked in and out on by the DCLK. For details on the serial
port timing please see the timing diagram in the section on A.C. characteristics.
125uS
FSC
DIN
DOUT
32 bits
DOUT is open-collector, it should be pulled high with an external pull-up resistor. Outside the 32
bit data transfer window, DOUT pins can be forced to drive low by setting bit 3 in register 0x01.
This option allows certain types of peripherals to activate the data clock.
Tiger500 mode: Serial port data transfer
Tiger560 USB Endpoint 3 and Endpoint 4 are used for the serial port data transfer. Each pipe will
transfer 37 bytes of data each USB isochronous transfer. Endpoint 3 will communicate the serial
port data back to host and Endpoint 4 will transfer output data to serial port.
The serial port clock is asynchronous to the USB clock, so an adaptive endpoint design is used.
Endpoint 3 provides the data rate information and feedback to the host. Host receives the data
rate information and decides the transfer rate to Endpoint 4. The data rate information is in the
byte one of the transferred data stream. Three possible value are defined, 32, 28 and 36. For 8
KHz of frame clock, every 1 ms, 32 bytes of data will be transferred. Endpoint 3 will adjust the
transfer count with either 28 or 36 based on the difference between the serial port clock and USB
clock.
The host is required to send the same amount of data to Endpoint 4 for the synchronization. Both
endpoints have the same data format. The first byte is the number of valid data bytes. The
following bytes are the valid data. Stuff bytes are attached at end of valid data so the total number
of bytes is 37.
Revision 1.1 released on 2/20/01
Page 17