SA24C1024 Datasheet, PDF (16/27 Pages) List of Unclassifed Manufacturers – 1024Kb EEPROM IIC

Device Operation
The SA24C1024 supports a bidirectional
bus-oriented protocol, which defines any
device that sends data onto the bus as a
transmitter and the receiving device as the
receiver. The device controlling the transfer
is defined as the Master and the device
that is controlled is the Slave. The Master
always initiates data transfers and provides
the clock for both transmit and receive
operations. The SA24C1024 is therefore
considered to be the Slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change
only during SCL LOW. SDA state changes
during SCL HIGH are reserved for
indicating START and STOP conditions.
For more details, see Figure 10.
SA24C1024 Datasheet
SAIFUN
16
START Condition
All commands are preceded by the START
condition, which is a HIGH-to-LOW
transition of SDA when SCL is HIGH. The
SA24C1024 continuously monitors the
SDA and SCL lines for the START
condition and does not respond to any
command until this condition has been met.
For more details, see Figure 11.
STOP Condition
All communications are terminated by a
STOP condition, which is a LOW-to-HIGH
transition of SDA when SCL is HIGH. The
STOP condition is also used by the
SA24C1024 to place the device in the
standby power mode. For more details, see
Figure 11.
SA24C1024 Array Addressing
During Read/Write operations, addressing
the EEPROM memory array involves
providing the Slave address with the Most
Significant Address bit (add16), as well as
two address bytes, Word Address 1 and
Word Address 0. The Word Address 1 byte
contains the 8 MSBs of the array address,
while the Word Address 0 byte contains
the 8 LSBs of the array address.