SA24C1024 Datasheet, PDF (12/27 Pages) List of Unclassifed Manufacturers – 1024Kb EEPROM IIC

Background Information
(IIC Bus)
Extended IIC specification is an extension
of the Standard IIC specification, which
enables addressing of EEPROMs with
more than 15 Kbits of memory on an IIC
bus. The difference between the two
specifications is that the Extended IIC
specification defines two bytes of Array
Address information, while the Standard
IIC specification defines only one. All other
aspects are identical between the two
specifications. Using two bytes of the array
address, one Device/Page Block selection
bit (A1) in the Slave address byte and one
address signal (add16) in the Slave
address, it is possible to address up to 2
Mbits (2⁸ • 2⁸ • 2 • 2 • 8 = 2 Mbits) of
memory on an IIC bus.
Note that, due to format difference, it is not
possible to have both peripherals that
follow the Standard IIC specification (for
example, 16Kbit EEPROM) and peripherals
that follow the Extended IIC specification
(for example, 1024Kbit EEPROM) on a
common IIC bus.
The IIC bus allows synchronous
bidirectional communication between a
transmitter and a receiver using a Clock
signal (SCL) and a Data signal (SDA).
Additionally, there is one Address signal
(A1) that collectively serves as "chip select
signal" to a device (for example, EEPROM)
on the bus.
SA24C1024 Datasheet
SAIFUN
12
All communication on the IIC bus must be
started with a valid START condition (by
the Master), followed by transmittal (also
by the Master) of byte(s) of information
(Address/Data). For every byte of
information received, the addressed
receiver provides a valid acknowledge
(ACK) pulse to further continue the
communication (unless the receiver intends
to discontinue the communication).
Depending on the direction of transfer
(Write or Read), the receiver can either be
a Slave or the Master. A typical IIC
communication concludes with a STOP
condition by the Master.
Addressing an EEPROM memory location
involves sending a command string with
the following information:
[DEVICE TYPE]—[DEVICE/PAGE BLOCK
SELECTION (including ARRAY MSB
ADDRESS BIT (add16)]—[R/WBIT]—
[ARRAY ADDRESS Byte #1]—[ARRAY
ADDRESS Byte #0]
Slave Address
The Slave address is an 8-bit information
consisting of a Device Type field (4 bits), a
Device/Page Block selection field (3 bits)
and one Read/Write bit.
Device Type
Identifier
Device/Page
Block Selection
1 0 1 0 0 A1 Add16 R/W (LSB)
Figure 9. Slave Address